diff options
Diffstat (limited to 'power-sequencer-pcb/rev-a/power-sequencer-pcb-B_Cu.gbr')
| -rw-r--r-- | power-sequencer-pcb/rev-a/power-sequencer-pcb-B_Cu.gbr | 489 |
1 files changed, 489 insertions, 0 deletions
diff --git a/power-sequencer-pcb/rev-a/power-sequencer-pcb-B_Cu.gbr b/power-sequencer-pcb/rev-a/power-sequencer-pcb-B_Cu.gbr new file mode 100644 index 0000000..d8dbca3 --- /dev/null +++ b/power-sequencer-pcb/rev-a/power-sequencer-pcb-B_Cu.gbr @@ -0,0 +1,489 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,9.0.5*% +%TF.CreationDate,2025-10-13T17:13:28+02:00*% +%TF.ProjectId,power-sequencer-pcb,706f7765-722d-4736-9571-75656e636572,A*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L4,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 9.0.5) date 2025-10-13 17:13:28* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%TA.AperFunction,ComponentPad*% +%ADD10C,3.000000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD12RoundRect,0.250000X0.550000X-0.550000X0.550000X0.550000X-0.550000X0.550000X-0.550000X-0.550000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13O,1.500000X1.050000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD14R,1.500000X1.050000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD15C,2.500000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD16R,1.800000X1.800000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD17O,2.000000X2.000000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD18C,1.524000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD19R,1.700000X1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD20C,1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD21RoundRect,0.250000X-0.750000X0.600000X-0.750000X-0.600000X0.750000X-0.600000X0.750000X0.600000X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD22O,2.000000X1.700000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD23R,1.600000X1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD24O,1.800000X1.800000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD25C,2.000000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD26C,3.000000*% +%TD*% +G04 APERTURE END LIST* +D10* +%TO.P,J1,1,Pin_1*% +%TO.N,Net-(J1-Pin_1)*% +X86307500Y-78095000D03* +%TO.P,J1,2,Pin_2*% +%TO.N,AC_N*% +X86307500Y-69595000D03* +%TD*% +%TO.P,J2,1,Pin_1*% +%TO.N,Net-(J2-Pin_1)*% +X86307500Y-96595000D03* +%TO.P,J2,2,Pin_2*% +%TO.N,AC_N*% +X86307500Y-88095000D03* +%TD*% +%TO.P,J4,1,Pin_1*% +%TO.N,Net-(J4-Pin_1)*% +X86307500Y-133595000D03* +%TO.P,J4,2,Pin_2*% +%TO.N,AC_N*% +X86307500Y-125095000D03* +%TD*% +%TO.P,J3,1,Pin_1*% +%TO.N,Net-(J3-Pin_1)*% +X86307500Y-115095000D03* +%TO.P,J3,2,Pin_2*% +%TO.N,AC_N*% +X86307500Y-106595000D03* +%TD*% +D11* +%TO.P,R2,2*% +%TO.N,Net-(U1-GPIO2{slash}SCK)*% +X120595000Y-98675000D03* +%TO.P,R2,1*% +%TO.N,Net-(Q1-B)*% +X120595000Y-88515000D03* +%TD*% +%TO.P,D1,2,A*% +%TO.N,Net-(D1-A)*% +X115595000Y-90785000D03* +D12* +%TO.P,D1,1,K*% +%TO.N,+5V*% +X115595000Y-98405000D03* +%TD*% +D13* +%TO.P,Q1,3,C*% +%TO.N,Net-(D1-A)*% +X115140000Y-86270000D03* +%TO.P,Q1,2,B*% +%TO.N,Net-(Q1-B)*% +X115140000Y-85000000D03* +D14* +%TO.P,Q1,1,E*% +%TO.N,DC_GND*% +X115140000Y-83730000D03* +%TD*% +D11* +%TO.P,R3,1*% +%TO.N,Net-(Q2-B)*% +X122000000Y-107420000D03* +%TO.P,R3,2*% +%TO.N,Net-(U1-GPIO4{slash}MISO)*% +X122000000Y-117580000D03* +%TD*% +D12* +%TO.P,D3,1,K*% +%TO.N,+5V*% +X115000000Y-135810000D03* +D11* +%TO.P,D3,2,A*% +%TO.N,Net-(D3-A)*% +X115000000Y-128190000D03* +%TD*% +D10* +%TO.P,K2,1*% +%TO.N,AC_L*% +X108950000Y-110050000D03* +D15* +%TO.P,K2,2*% +%TO.N,Net-(D2-A)*% +X107000000Y-104000000D03* +D10* +%TO.P,K2,3*% +%TO.N,Net-(J3-Pin_1)*% +X94800000Y-104000000D03* +%TO.P,K2,4*% +%TO.N,unconnected-(K2-Pad4)*% +X94750000Y-116050000D03* +D15* +%TO.P,K2,5*% +%TO.N,+5V*% +X107000000Y-116000000D03* +%TD*% +D16* +%TO.P,RV1,1*% +%TO.N,AC_L*% +X113000000Y-76750000D03* +D17* +%TO.P,RV1,2*% +%TO.N,AC_N*% +X113000000Y-69250000D03* +%TD*% +D12* +%TO.P,C1,1*% +%TO.N,+5V*% +X128500000Y-112455113D03* +D11* +%TO.P,C1,2*% +%TO.N,DC_GND*% +X128500000Y-110455113D03* +%TD*% +D18* +%TO.P,U1,1,GPIO26/ADC0/A0*% +%TO.N,unconnected-(U1-GPIO26{slash}ADC0{slash}A0-Pad1)*% +X143120000Y-136851500D03* +%TO.P,U1,2,GPIO27/ADC1/A1*% +%TO.N,unconnected-(U1-GPIO27{slash}ADC1{slash}A1-Pad2)*% +X143120000Y-134311500D03* +%TO.P,U1,3,GPIO28/ADC2/A2*% +%TO.N,unconnected-(U1-GPIO28{slash}ADC2{slash}A2-Pad3)*% +X143120000Y-131771500D03* +%TO.P,U1,4,GPIO29/ADC3/A3*% +%TO.N,unconnected-(U1-GPIO29{slash}ADC3{slash}A3-Pad4)*% +X143120000Y-129231500D03* +%TO.P,U1,5,GPIO6/SDA*% +%TO.N,unconnected-(U1-GPIO6{slash}SDA-Pad5)*% +X143120000Y-126691500D03* +%TO.P,U1,6,GPIO7/SCL*% +%TO.N,BUTTON*% +X143120000Y-124151500D03* +%TO.P,U1,7,GPIO0/TX*% +%TO.N,LED*% +X143120000Y-121611500D03* +%TO.P,U1,8,GPIO1/RX*% +%TO.N,unconnected-(U1-GPIO1{slash}RX-Pad8)*% +X127880000Y-121611500D03* +%TO.P,U1,9,GPIO2/SCK*% +%TO.N,Net-(U1-GPIO2{slash}SCK)*% +X127880000Y-124151500D03* +%TO.P,U1,10,GPIO4/MISO*% +%TO.N,Net-(U1-GPIO4{slash}MISO)*% +X127880000Y-126691500D03* +%TO.P,U1,11,GPIO3/MOSI*% +%TO.N,Net-(U1-GPIO3{slash}MOSI)*% +X127880000Y-129231500D03* +%TO.P,U1,12,3V3*% +%TO.N,+3V3*% +X127880000Y-131771500D03* +%TO.P,U1,13,GND*% +%TO.N,DC_GND*% +X127880000Y-134311500D03* +%TO.P,U1,14,VBUS*% +%TO.N,+5V*% +X127880000Y-136851500D03* +%TD*% +D12* +%TO.P,D2,1,K*% +%TO.N,+5V*% +X115000000Y-117310000D03* +D11* +%TO.P,D2,2,A*% +%TO.N,Net-(D2-A)*% +X115000000Y-109690000D03* +%TD*% +D10* +%TO.P,K3,1*% +%TO.N,AC_L*% +X108950000Y-128550000D03* +D15* +%TO.P,K3,2*% +%TO.N,Net-(D3-A)*% +X107000000Y-122500000D03* +D10* +%TO.P,K3,3*% +%TO.N,Net-(J4-Pin_1)*% +X94800000Y-122500000D03* +%TO.P,K3,4*% +%TO.N,unconnected-(K3-Pad4)*% +X94750000Y-134550000D03* +D15* +%TO.P,K3,5*% +%TO.N,+5V*% +X107000000Y-134500000D03* +%TD*% +D11* +%TO.P,R4,1*% +%TO.N,Net-(Q3-B)*% +X122000000Y-125920000D03* +%TO.P,R4,2*% +%TO.N,Net-(U1-GPIO3{slash}MOSI)*% +X122000000Y-136080000D03* +%TD*% +D10* +%TO.P,K1,1*% +%TO.N,AC_L*% +X108950000Y-91550000D03* +D15* +%TO.P,K1,2*% +%TO.N,Net-(D1-A)*% +X107000000Y-85500000D03* +D10* +%TO.P,K1,3*% +%TO.N,Net-(J2-Pin_1)*% +X94800000Y-85500000D03* +%TO.P,K1,4*% +%TO.N,unconnected-(K1-Pad4)*% +X94750000Y-97550000D03* +D15* +%TO.P,K1,5*% +%TO.N,+5V*% +X107000000Y-97500000D03* +%TD*% +D14* +%TO.P,Q3,1,E*% +%TO.N,DC_GND*% +X118000000Y-120500000D03* +D13* +%TO.P,Q3,2,B*% +%TO.N,Net-(Q3-B)*% +X118000000Y-121770000D03* +%TO.P,Q3,3,C*% +%TO.N,Net-(D3-A)*% +X118000000Y-123040000D03* +%TD*% +D19* +%TO.P,SW1,1,1*% +%TO.N,DC_GND*% +X135500000Y-112000000D03* +D20* +%TO.P,SW1,2,2*% +%TO.N,BUTTON*% +X138040000Y-112000000D03* +%TO.P,SW1,3,K*% +%TO.N,DC_GND*% +X140580000Y-112000000D03* +%TO.P,SW1,4,A*% +%TO.N,LED*% +X143120000Y-112000000D03* +%TD*% +D21* +%TO.P,PS1,1,AC/L*% +%TO.N,AC_L*% +X136500000Y-61712500D03* +D22* +%TO.P,PS1,2,AC/N*% +%TO.N,AC_N*% +X131500000Y-61712500D03* +%TO.P,PS1,3,-Vout*% +%TO.N,DC_GND*% +X141500000Y-90792500D03* +%TO.P,PS1,4,+Vout*% +%TO.N,+5V*% +X126500000Y-90792500D03* +%TD*% +D11* +%TO.P,R1,1*% +%TO.N,BUTTON*% +X136080000Y-116500000D03* +%TO.P,R1,2*% +%TO.N,+3V3*% +X125920000Y-116500000D03* +%TD*% +D23* +%TO.P,F1,1*% +%TO.N,Net-(J1-Pin_1)*% +X95000000Y-77000000D03* +D24* +%TO.P,F1,2*% +%TO.N,Net-(SW2-A)*% +X95000000Y-69000000D03* +%TD*% +D14* +%TO.P,Q2,1,E*% +%TO.N,DC_GND*% +X116640000Y-103230000D03* +D13* +%TO.P,Q2,2,B*% +%TO.N,Net-(Q2-B)*% +X116640000Y-104500000D03* +%TO.P,Q2,3,C*% +%TO.N,Net-(D2-A)*% +X116640000Y-105770000D03* +%TD*% +D23* +%TO.P,SW2,1,A*% +%TO.N,Net-(SW2-A)*% +X103500000Y-69000000D03* +D24* +%TO.P,SW2,2,B*% +%TO.N,AC_L*% +X103500000Y-77000000D03* +%TD*% +D25* +%TO.N,AC_L*% +X113000000Y-76750000D02* +X123817824Y-76750000D01* +X123817824Y-76750000D02* +X136701000Y-63866824D01* +X136701000Y-63866824D02* +X136701000Y-61712500D01* +%TO.N,AC_N*% +X113000000Y-69250000D02* +X123962500Y-69250000D01* +X123962500Y-69250000D02* +X131299000Y-61913500D01* +X131299000Y-61913500D02* +X131299000Y-61712500D01* +D26* +X86307500Y-69595000D02* +X86307500Y-67473680D01* +X86307500Y-67473680D02* +X90982180Y-62799000D01* +X90982180Y-62799000D02* +X106549000Y-62799000D01* +X106549000Y-62799000D02* +X113000000Y-69250000D01* +%TO.N,Net-(SW2-A)*% +X95000000Y-69000000D02* +X103500000Y-69000000D01* +%TO.N,Net-(J1-Pin_1)*% +X86307500Y-78095000D02* +X93905000Y-78095000D01* +X93905000Y-78095000D02* +X95000000Y-77000000D01* +%TO.N,AC_L*% +X103500000Y-77000000D02* +X112750000Y-77000000D01* +X112750000Y-77000000D02* +X113000000Y-76750000D01* +X103500000Y-77000000D02* +X101049000Y-79451000D01* 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